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| INTEGRATED CIRCUITS DATA SHEET TDA4885 150 MHz video controller with I2C-bus Product specification Supersedes data of 1997 Mar 19 File under Integrated Circuits, IC02 1997 Nov 25 Philips Semiconductors Product specification 150 MHz video controller with I2C-bus CONTENTS 1 2 3 4 5 6 7 7.1 7.2 7.2.1 7.2.2 7.2.3 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 8 9 10 11 12 13 13.1 13.2 14 15 15.1 15.2 15.3 16 17 18 FEATURES GENERAL DESCRIPTION ORDERING INFORMATION QUICK REFERENCE DATA BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION Signal input stage (input clamping, blanking and clipping) Electronic potentiometer stages Contrast control (driven by I2C-bus, 6-bit DAC) Brightness control (driven by I2C-bus, 6-bit DAC) Gain control (driven by I2C-bus, 6-bit DAC) and grey scale tracking Output stage Pedestal blanking Output clamping, feedback references and DAC outputs Clamping and blanking pulses On Screen Display (OSD) Limiting by contrast reduction Gain modulation I2C-bus control LIMITING VALUES THERMAL CHARACTERISTICS CHARACTERISTICS I2C-BUS PROTOCOL INTERNAL CIRCUITRY TEST AND APPLICATION INFORMATION Test application Recommendations for building the application board PACKAGE OUTLINE SOLDERING Introduction Soldering by dipping or by wave Repairing soldered joints DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE OF PHILIPS I2C COMPONENTS TDA4885 1997 Nov 25 2 Philips Semiconductors Product specification 150 MHz video controller with I2C-bus 1 FEATURES 2 GENERAL DESCRIPTION TDA4885 * 150 MHz pixel rate * 2.7 ns rise time * Gain modulation capability for brightness uniformity * I2C-bus control * Grey scale tracking * On Screen Display (OSD) mixing * Negative feedback for DC-coupled cathodes * Positive feedback for AC-coupled cathodes * DAC outputs for black level restoration with AC-coupled cathodes * Integrated black level storage capacitors * Beam current limiting * Analog subcontrast setting * Pedestal blanking * OSD contrast * Sync clipping. 3 ORDERING INFORMATION TYPE NUMBER TDA4885 The TDA4885 is a monolithic integrated RGB pre-amplifier for colour monitor systems (e.g. 15" and 17") with I2C-bus control and OSD. In addition to bus control beam current limiting and gain modulation are possible. The signals are amplified in order to drive commonly used video modules or discrete solutions. Individual black level control with negative feedback from the cathode (DC coupling) or fixed black level control with positive feedback and 3 DAC outputs for external cut-off control (AC coupling) is possible. With special advantages the circuit can be used in conjunction with the TDA485x monitor deflection IC family. PACKAGE NAME SDIP32 DESCRIPTION plastic shrink dual in-line package; 32 leads (400 mil) VERSION SOT232-1 1997 Nov 25 3 Philips Semiconductors Product specification 150 MHz video controller with I2C-bus 4 QUICK REFERENCE DATA SYMBOL VP IP VP1, 2, 3 IP1, 2, 3 Vi(b-w) Vo(b-w) PARAMETER supply voltage (pin 7) supply current (pin 7) channel supply voltage (pins 29, 24 and 19) channel supply current (pins 29, 24 and 19) input voltage (black-to-white value; pins 6, 8 and 10) nominal output voltage swing (black-to-white value; pins 30, 25 and 20) maximum output voltage swing (black-to-white value; pins 30, 25 and 20) output voltage level (pins 30, 25 and 20) typical reference black level (pins 30, 25 and 20) peak output sink current peak output source current bandwidth video rise time at signal outputs (pins 30, 25 and 20) over/undershoot at signal outputs (pins 30, 25 and 20) crosstalk at signal outputs (pins 30, 25 and 20) contrast control related to nominal contrast gain control related to maximum gain brightness control (typical black level voltage change related to output signal amplitude) maximum OSD contrast; maximum gain; pins 12, 13 and 14 grounded minimum rise/fall time f = 80 MHz nominal contrast; maximum gain; pins 12, 13 and 14 grounded maximum contrast; maximum gain; pins 12, 13 and 14 grounded CONDITIONS MIN. 7.6 - 7.6 - - 2.5 TDA4885 TYP. MAX. UNIT 8.0 20 8.0 40 0.7 2.8 8.8 25 8.8 - 1.0 - V mA V mA V V Vo(b-w)(max) - 4.5 - V Vo Vbl Io(sink) Io(source) B tr(O) dVO ct CC GC BC 0.1 0.5 during fast signal transients - during fast signal transients -40 -3 dB (small signal) - - - - -28 -7 -10 - - - - - 150 2.7 5 -30 - - - 125 6.0 2.5 20 - - - - - +4 0 +30 - V V mA mA MHz ns % dB dB dB % % Vo(OSD)(max) maximum OSD output voltage swing related to nominal output voltage swing (pins 30, 25 and 20) COSD OSD contrast control related to maximum OSD contrast -12 - 0 dB 1997 Nov 25 4 5 ok, full pagewidth 1997 Nov 25 SDA 15 data 16 12 13 14 SCL GM1 GM2 GM3 I2C-BUS MODULATION 8-BIT DAC REF3 27 REF2 8-BIT DAC 8-BIT DAC CHANNEL 3 REFERENCE 22 LIM 17 Philips Semiconductors BLOCK DIAGRAM 6-BIT DAC 6-BIT DAC REGISTER FPOL 6-BIT DAC POLARITY SWITCH 29 signal path 1 GAIN 30 BRIGHTNESS PEDESTAL BLANKING 28 31 24 signal path 2 GAIN 25 OSDCONTRAST BRIGHTNESS PEDESTAL BLANKING 23 26 PEDST signal path 3 GAIN 20 OSDCONTRAST BRIGHTNESS blanking input clamping PEDST SUPPLY OSD-INPUT DISO INPUT CLAMPING VERTICAL BLANKING 5 CLI DISV BLANKING OUTPUT CLAMPING 11 HFB 7 VP 9 MHA343 LIMITING FPOL DISV CHANNEL 1 REFERENCE DISO PEDST 6-BIT DAC 32 6-BIT DAC REF1 VP1 4-BIT DAC BLANKING CHANNEL 2 REFERENCE VI1 OSDCONTRAST 6 CONTRAST INPUTCLAMPING BLANKING CLIPPING VO1 GND1 FB1 VP2 PEDST 150 MHz video controller with I2C-bus VI2 8 CONTRAST INPUTCLAMPING BLANKING CLIPPING VO2 GND2 19 FB2 VP3 5 PEDESTAL BLANKING VI3 10 CONTRAST INPUTCLAMPING BLANKING CLIPPING VO3 18 21 GND3 FB3 fast blanking TDA4885 1 OSD1 OSD2 OSD3 2 3 4 FBL GND Product specification TDA4885 Fig.1 Block diagram. Philips Semiconductors Product specification 150 MHz video controller with I2C-bus 6 PINNING PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 DESCRIPTION fast blanking input for OSD insertion OSD input channel 1 OSD input channel 2 OSD input channel 3 vertical blanking input (input clamping) signal input channel 1 supply voltage signal input channel 2 ground signal input channel 3 horizontal flyback input (output clamping, blanking) gain modulation input channel 1 gain modulation input channel 2 gain modulation input channel 3 I2C-bus serial data input/output I2C-bus clock input beam current limiting input, subcontrast setting ground channel 3 supply voltage channel 3 signal output channel 3 feedback input channel 3 reference voltage channel 3 ground channel 2 supply voltage channel 2 signal output channel 2 feedback input channel 2 reference voltage channel 2 ground channel 1 supply voltage channel 1 signal output channel 1 feedback input channel 1 reference voltage channel 1 Fig.2 Pin configuration. OSD1 OSD2 OSD3 CLI VI1 VP VI2 GND 2 3 4 5 6 7 8 handbook, halfpage TDA4885 SYMBOL FBL OSD1 OSD2 OSD3 CLI VI1 VP VI2 GND VI3 HFB GM1 GM2 GM3 SDA SCL LIM GND3 VP3 VO3 FB3 REF3 GND2 VP2 VO2 FB2 REF2 GND1 VP1 VO1 FB1 REF1 FBL 1 32 REF1 31 FB1 30 VO1 29 VP1 28 GND1 27 REF2 26 FB2 TDA4885 9 25 VO2 24 VP2 23 GND2 22 REF3 21 FB3 20 VO3 19 VP3 18 GND3 17 LIM VI3 10 HFB 11 GM1 12 GM2 13 GM3 14 SDA 15 SCL 16 MHA342 1997 Nov 25 6 Philips Semiconductors Product specification 150 MHz video controller with I2C-bus 7 FUNCTIONAL DESCRIPTION 7.2.3 TDA4885 GAIN CONTROL (DRIVEN BY I2C-BUS, 6-BIT DAC) AND GREY SCALE TRACKING See block diagram (Fig.1) and definition of levels and output signals (Chapter "Characteristics" notes 1 to 3; Figs 3 to 6). 7.1 Signal input stage (input clamping, blanking and clipping) The RGB input signals with nominal signal amplitude of 0.7Vb-w are capacitively coupled into the TDA4885 from a low-ohmic source (75 recommended) and actively clamped to an internal DC voltage during signal black level. Because of the high-ohmic input impedance of the TDA4885 the coupling capacitor (which also functions as storage capacitor during clamping pulses) can be relatively small (10 nF recommended). The internal leakage currents will discharge the coupling capacitor resulting in black output signals for missing input clamping pulses. Composite signals will not disturb normal operations because a clipping circuit cuts all signal parts below black level. A fast signal blanking stage belongs to the input stage which is driven by several blanking pulses (see Section "Clamping and blanking pulses") and control bit DISV = 1. During the off condition the internal reference black level will be inserted instead of the input signals. 7.2 7.2.1 Electronic potentiometer stages CONTRAST CONTROL (DRIVEN BY I2C-BUS, 6-BIT DAC) Gain control is used for white point adjustment (correction for different voltage to light amplification of the three colour channels) and therefore individual for the three channels. The video signals related to the reference black level can be gain controlled within a range of typical 7 dB. The nominal setting is maximum gain. The video signal is the addition of the contrast controlled input signal and the brightness shift. The gain setting is also valid for OSD signals, thus the complete `grey scale' is effected by gain control. 7.3 Output stage In the output stage the nominal input signal will be amplified to 2.8Vb-w output colour signal at nominal contrast and maximum gain. The maximum input-output amplification at maximum contrast and gain settings is 16 dB. By output clamping the reference black level can be adjusted. In order to achieve very fast rise and fall times of the output signals with minimum crosstalk between the channels, each output stage has its own supply voltage and ground pin. 7.4 Pedestal blanking The input signals related to the internal reference black level can be simultaneously adjusted by contrast control with a control range of typically 32 dB. The nominal contrast setting is defined for 26H (4 dB below maximum). 7.2.2 BRIGHTNESS CONTROL (DRIVEN BY I2C-BUS, 6-BIT DAC) For the video portion the reference black level should correspond to the `extended cut-off voltage' at the cathode. During vertical flyback nevertheless retrace lines may be visible, though blanking to spot cut-off is useful. With control bit PEDST = 1 the pedestal black level will be adjusted by output clamping instead of the reference black level (see Fig.5). The pedestal black level is more negative than the video black level at minimum brightness setting and the voltage difference to reference black level is independent of any user control. 7.5 Output clamping, feedback references and DAC outputs With brightness control the video black level will be shifted in relation to the reference black level simultaneously for all three channels. With a negative setting (maximum 10% of nominal signal amplitude) dark signal parts will be lost in ultra black while for positive settings (maximum 30% of nominal signal amplitude) the background will alter from black to grey. The nominal brightness setting (10H) is no shift. The brightness setting is also valid for OSD signals. During blanking and output clamping the video black level will be blanked to reference black level (brightness blanking). Aim of the output clamping (pins FB1, FB2 and FB3) is to set the reference black level of the signal outputs to a value which corresponds to the `extended cut-off voltage' of the CRT cathodes. At lack of output clamping pulses the integrated storage capacitors will discharge resulting in output signals going to switch-off voltage. Feedback references are driven by the I2C-bus. 1997 Nov 25 7 Philips Semiconductors Product specification 150 MHz video controller with I2C-bus 1. Control bit FPOL = 0 The cathode voltage (DC-coupled) is divided by a voltage divider and fed back to the IC. During the output clamping pulse it is compared with an adjustable feedback reference voltage with a range of 5.8 to 4.0 V. Any difference will lead to a reference black level correction (control bit PEDST = 0) or pedestal black level correction (control bit PEDST = 1) by charging or discharging the integrated capacitor which stores the black level information between the output clamping pulses. The DC voltages of the output stages should be designed in such a way that the reference black level/pedestal black level is within the range of 0.5 to 2.5 V. The reference voltages are also fed to the DAC output pins (REF1, REF2 and REF3). For correct operation it is necessary that there is enough room for ultra black signals (negative brightness setting, pedestal black level if control bit PEDST = 1). Any clipping with the video supply voltage can disturb signal rise/fall times or the black level stabilization. 2. Control bit FPOL = 1 For applications with AC-coupled cathodes positive feedback can be taken directly or divided by a voltage divider from the signal outputs or the emitter of an external emitter follower. During the output clamping pulse it is compared with a fixed reference voltage of 0.7 V. For black level restoration the DAC outputs (REF1, REF2 and REF3) with a range of 5.8 to 4.0 V can be used. The use of pedestal blanking allows a very simple black level restoration with a DC diode clamp instead of a complicated pulse restoration circuit because the pedestal black level is the most negative output signal. 7.6 Clamping and blanking pulses TDA4885 During the vertical blanking pulse at pin CLI signal blanking, brightness blanking and with control bit PEDST = 1 pedestal blanking will be activated. Input clamping pulses during vertical blanking will not switch off blanking. For proper input clamping the input signals have to be at black level during the input clamping pulse. An input pulse at pin HFB (e.g. horizontal flyback pulse) will be scanned with two thresholds. If the input pulse exceeds the first one (typical 1.4 V) signal blanking, brightness blanking and if control bit PEDST = 1 pedestal blanking will be activated. If the input pulse exceeds the second one (typical 3 V) additionally output clamping will be activated. The vertical blanking pulse can also be mixed with the horizontal flyback pulse at pin HFB. 7.7 On Screen Display (OSD) If the fast blanking input signal at pin FBL exceeds the threshold (typical 1.4 V) the input signals are blanked (signal blanking) and OSD signals are enabled. Then any signal at pins OSD1, OSD2 or OSD3 exceeding the same threshold will create an insertion signal with an amplitude of 125% of the nominal colour signal (approximately 80% of the maximum colour signal). The amplitude can be controlled by OSD contrast (driven by I2C-bus) with a range of 12 dB. The OSD signals are inserted at the same point as the contrast controlled input signals and will be treated with brightness and gain control like normal input signals. With control bit DISO = 1 OSD, signal insertion and fast blanking (pin FBL) are disabled. 7.8 Limiting by contrast reduction The pin CLI of TDA4885 can be directly connected to pin CLBL of e.g. TDA4855 sync processor for input clamping pulses and vertical blanking pulses. The threshold for the input clamping pulse (typical 3 V) is higher than the threshold for the vertical blanking pulse (typical 1.4 V) but there must be no blanking during input clamping. Thus vertical blanking only is enabled if no input clamping is detected. For this reason the input clamping pulse must have rise/fall times faster than 75 ns/V during the transition from 1.2 to 3.5 V and opposite. The internal vertical blanking pulse will be delayed by typical 290 ns. Beam current limiting is possible with an external voltage at pin LIM. The maximum overall voltage gain of contrast (and OSD contrast) control can be reduced by a voltage between 4.5 V (start of reduction) and 2.0 V (-26 dB) without effecting the contrast bit resolution. By setting the maximum voltage at pin LIM to less than 4.5 V the maximum gain is reduced for all channels (subcontrast setting). The open-circuit pin will have a voltage of approximately 5.0 V but is very high-ohmic and should be tied to a voltage source of 5.0 V or higher or should be connected to a capacitance of some nF if not used. 1997 Nov 25 8 Philips Semiconductors Product specification 150 MHz video controller with I2C-bus 7.9 Gain modulation TDA4885 To achieve brightness uniformity over the screen scan dependent gain modulation is possible. With open-circuit pins the gain will be reduced by 20% giving the possibility of symmetrical gain modulations (18%) with 1 V related to the open-circuit voltage of about 2.0 V at any gain setting. If the gain modulation feature will not be used pins GM1, GM2 and GM3 should be grounded to profit by maximum voltage gain. 7.10 I2C-bus control The TDA4885 contains an I2C-bus receiver for several control functions: 1. Contrast control with 6-bit DAC 2. Brightness control with 6-bit DAC 3. OSD contrast control with 4-bit DAC 4. Gain control for each channel with 6-bit DAC 5. Internal feedback reference and external reference voltage control for each channel with 8-bit DAC 6. Control register with control bits FPOL, DISV, DISO and PEDST 7. Test register for production tests only. All registers are set to logic 0 (minimum value for control registers) after power-up and after internal power-on reset of the I2C-bus. 1997 Nov 25 9 Philips Semiconductors Product specification 150 MHz video controller with I2C-bus 8 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VP VP1, 2, 3 Vi Vext PARAMETER supply voltage (pin 7) input voltage (pins 6, 8 and 10) external DC voltage applied to the following pins: pins 1 to 4 pins 12, 13, 14 and 17 pins 11 and 5 pins 15 and 16 pins 31, 26 and 21 pins 30, 25 and 20 pins 32, 27 and 22 Io(av) IOM Ptot Tstg Tamb Tj VESD average output current (pins 30, 25 and 20) peak output current (pins 30, 25 and 20) total power dissipation storage temperature operating ambient temperature junction temperature electrostatic handling for all pins machine model 0.75 H (note 2) human body model (note 3) Notes 1. No external voltages. 2. Equivalent to discharging a 200 pF capacitor via a 10 series resistor ("UZW-B0/FQ-B302"). 3. Equivalent to discharging a 100 pF capacitor via a 1500 series resistor ("UZW-B0/FQ-A302"). 9 THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER thermal resistance from junction to ambient CONDITIONS in free air VALUE 60 -250 -3000 +250 +3000 -0.1 -0.1 -0.1 -0.1 -0.1 note 1 -0.1 - - - -25 -20 -25 VP VP VP + 0.7 VP VP + 0.7 note 1 VP 20 50 1300 +150 +70 +150 0 -0.1 supply voltage channel 1, 2 and 3 (pins 29, 24 and 19) 0 MIN. 8.8 8.8 VP MAX. TDA4885 UNIT V V V V V V V V V mA mA mW C C C V V UNIT K/W 1997 Nov 25 10 Philips Semiconductors Product specification 150 MHz video controller with I2C-bus TDA4885 10 CHARACTERISTICS All voltages and currents are measured in test circuit of Fig.19; all voltages are measured with respect to GND (pins 9, 28, 23 and 18); VP = VP1, 2, 3 = 8 V (pins 7, 29, 24 and 19); Tamb = 25 C; nominal input signals [0.7 V (peak-to-peak value) at pins 6, 8 and 10]; nominal colour signals at signal outputs (pins 30, 25 and 20); reference black level (Vrbl) approximately 0.7 V; nominal settings for brightness and contrast; maximum settings for OSD contrast and gain; no limiting of contrast (V17 = 5 V); no OSD fast blanking (pin 1 connected to ground); no gain modulation (pins 12, 13 and 14 connected to ground); notes 1 to 3; unless otherwise specified. SYMBOL Supply VP IP VP1, 2, 3 IP1, 2, 3 supply voltage (pin 7) supply current (pin 7) channel supply voltage (pins 29, 24 and 19) channel supply current (pins 29, 24 and 19) signal outputs (pins 30, 25 and 20) open-circuit; Vrbl = 0.7 V; note 5 note 4 7.6 - 7.6 - 8.0 20 8.0 40 8.8 25 8.8 45 V mA V mA PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VPSO supply voltage for signal switch signal outputs switched to off (threshold at pin 7) switch-off voltage; note 1 - - 7.2 V Clamping and blanking pulses (pins 5 and 11) V5 input clamping and vertical blanking input signal note 6 no blanking, no input clamping blanking, no input clamping input clamping, no blanking I5 input current V5 = 1 V; note 7 pin 5 grounded; note 7 V5 = -0.1 V; note 7 tr/f5 tW5 tdl5 rise/fall time for input clamping pulse, disable for blanking width of input clamping pulse delay between leading edges of vertical blanking input pulse and internal blanking pulse V11 < 0.8 V; input pulse with 50 ns/V; threshold for rising input pulse V5 = 1.4 V; threshold after input clamping pulse V5 = 3 V; see Fig.7 note 6; see Fig.7 -0.1 1.6 3.5 -1.5 -80 -250 - 0.6 - - - - -0.2 -60 - - 270 +1.2 2.6 VP -0.05 -30 75 - - V V V A A A ns/V s ns -200 -100 tdt5 delay between trailing edges of V11 < 0.8 V; input pulse with vertical blanking input pulse 50 ns/V; threshold V5 = 1.4 V; and internal blanking pulse see Fig.7 output clamping and blanking input signal note 8 no blanking, no output clamping blanking, no output clamping blanking, output clamping - 115 - ns V11 -0.1 2.0 3.5 - - - +0.8 2.6 VP V V V 1997 Nov 25 11 Philips Semiconductors Product specification 150 MHz video controller with I2C-bus TDA4885 SYMBOL I11 PARAMETER input current CONDITIONS V11 = 0.8 V; note 7 pin 5 grounded; note 7 V5 = -0.1 V; note 7 MIN. -3 -80 -250 - TYP. -0.4 -60 MAX. -0.1 -30 UNIT A A A -200 -100 Video signal inputs (channel 1: pin 6; channel 2: pin 8; channel 3: pin 10) Vi(b-w)6, 8, 10 VI(clamp)6, 8, 10 II6, 8, 10 positive input signal referred to black DC voltage during input clamping DC input current note 9 no input clamping; VI6, 8, 10 = VI(clamp)6, 8, 10; Tamb = -20 to +70 C during input clamping; VI6, 8, 10 = VI(clamp)6, 8, 10 0.7 V Zi6, 8, 10 Ci6, 8, 10 Signal blanking ct(bl) crosstalk suppression from input to output during blanking delay between blanking input (leading edge) and output signal blanking delay between blanking input (trailing edge) and output signal blanking control bit DISV = 1; f = 80 MHz 20 control bit DISV = 1; f = 135 MHz see Fig.8 10 - 30 15 55 - - - dB dB ns magnitude of signal input impedance input capacitance against ground f = 100 MHz; VI(DC)6, 8, 10 = VI(clamp)6, 8, 10 0.7 4 0.20 1.0 - 0.35 V V A - 0.02 110 500 - 150 190 - - - 3 A pF td11(sig)l td11(sig)t see Fig.8 - 25 - ns Clipping (measured at signal outputs) Vclipp offset during sync clipping VI6, 8, 10 = VI(clamp)6, 8, 10; related to nominal colour signal note 10; see Fig.3 - 1 2 % Contrast control; see Fig.9 and note 11 dC colour signal related to nominal 3FH (maximum) colour signal 26H (nominal) 00H (minimum) Gtrack tracking of output colour signals of channels 1, 2 and 3 3FH to 00H; note 12 - - - - 4 0 -28 0.0 - - - 0.5 dB dB dB dB 1997 Nov 25 12 Philips Semiconductors Product specification 150 MHz video controller with I2C-bus TDA4885 SYMBOL PARAMETER CONDITIONS MIN. TYP. - - MAX. UNIT Fast blanking (pin 1) and OSD signal insertion (channel 1: pin 2; channel 2: pin 3; channel 3: pin 4); note 13 V1 fast blanking input signal no video signal blanking, OSD signal insertion disabled video signal blanking, OSD signal insertion enabled V2, 3, 4 OSD input signal V1 > 1.7 V no internal OSD signal insertion internal OSD signal insertion tf(FBL) fall time of colour signals (pins 30, 25 and 20) rise time of colour signals (pins 30, 25 and 20) 0 1.7 - - - 1.1 VP - 1 10 V V ns 0 1.7 1.1 VP - 1 V V 90 to 10% amplitude; start of - fast blanking pulse at pin 1 with 1.2 ns/V; note 14; see Fig.10 10 to 90% amplitude; end of - fast blanking pulse at pin 1 with 1.2 ns/V; note 14; see Fig.10 - - tr(FBL) - 10 ns tr(OSD) tf(OSD) tg(CO) rise time of OSD colour signals 10 to 90% amplitude; input pulse with 1.2 ns/V; see Fig.10 fall time of OSD colour signals width of (negative going) OSD signal insertion glitch, leading edge width of (negative going) OSD signal insertion glitch, trailing edge overshoot/undershoot of OSD colour signal related to actual OSD output pulse amplitude time of OSD signal overshoot exceeding 10% 90 to 10% amplitude; input pulse with 1.2 ns/V; see Fig.10 - - - 4 7 6 ns ns ns identical pulses with 1.2 ns/V at - fast blanking input (pin 1) and OSD signal inputs (pins 2, 3 and 4); note 15; see Fig.10 identical pulses with 1.2 ns/V at - fast blanking input (pin 1) and OSD signal inputs (pins 2, 3 and 4); note 15; see Fig.10 OSD input pulse (pins 2, 3 - and 4) with 1.2 ns/V; V1 > 1.7 V OSD input pulse (pins 2, 3 - and 4) with 1.2 ns/V; V1 > 1.7 V tg(OC) - 6 ns dVOSD 13 20 % tover VOSD(max) - 125 2 150 ns % maximum OSD colour signal maximum OSD contrast; 100 related to nominal colour signal maximum gain; pins 12, 13 and 14 connected to ground -14 - OSD contrast control; see Fig.11 and note 16 dOC OSD colour signal related to maximum OSD colour signal 00H (minimum) 0FH (maximum) -12 0 -10 - dB dB 1997 Nov 25 13 Philips Semiconductors Product specification 150 MHz video controller with I2C-bus TDA4885 SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Limiting (pin 17); see Fig.9 and note 17 V17(nom) V17(start) V17(stop) I17 Vbl input voltage starting voltage for contrast and OSD contrast reduction stop voltage for contrast and OSD contrast reduction maximum input current -32 dB below maximum colour signal (contrast setting 3FH) V17 = 0 V 3FH (maximum) 10H (nominal) 00H (minimum) pin 17 open-circuit 4.7 4.2 1.5 -1.0 5.0 4.5 2.0 -0.5 5.3 4.8 2.5 -0.1 V V V A Brightness control; see Fig.12 and notes 18 and 19 difference between black level and reference black level at signal outputs related to nominal colour signal difference of Vbl between any two channels related to nominal colour signal +25 -2 -12 -1.2 +30 0 -10 0 +35 +2 -8 +1.2 % % % % VBT Brightness blanking td11(br)l delay between blanking input at pin 11 (leading edge) and brightness blanking at signal outputs delay between blanking input at pin 11 (trailing edge) and brightness blanking at signal outputs see Fig.8 - - 60 ns td11(br)t see Fig.8 - - 60 ns Gain control; see Fig.13 and note 20 dG video signal related to video signal at maximum gain 00H (minimum) 3FH (maximum) -8 - -7 0 - - 2.0 -6 - dB dB Gain modulation (channel 1: pin 12; channel 2: pin 13; channel 3: pin 14) V12, 13, 14 input voltage symmetrical modulation modulation feature not in use nominal: pins 12, 13 and 14 open-circuit Gmod1, 2, 3 gain modulation channels 1, 2 and 3 note 21; see Fig.14 pins 12, 13 and 14 grounded (modulation feature not in use) V12, 13, 14 = 1 V (maximum) V12, 13, 14 = 2 V V12, 13, 14 = 3 V (minimum) 112 120 130 % 1.0 - 1.8 3.0 0 2.2 V V V 112 - 76 118 100 82 124 - 88 % % % 1997 Nov 25 14 Philips Semiconductors Product specification 150 MHz video controller with I2C-bus TDA4885 SYMBOL Pedestal blanking V30, 25, 20PED PARAMETER CONDITIONS MIN. -18 TYP. -16 MAX. -14 UNIT difference of pedestal black level to video black level at nominal brightness at signal output pins related to nominal colour signal note 22; see Fig.5 % V30, 25, 20PED(T) variation of V30, 25, 20PED with temperature related to nominal colour signal Tamb = -20 to +70 C -0.8 0 +0.8 % Signal outputs (channel 1: pin 30; channel 2: pin 25; channel 3: pin 20) V30, 25, 20(b-w) nominal colour signal nominal contrast; maximum gain; pins 12, 13 and 14 grounded; VI(b-w) = 0.7 V; without load maximum contrast; maximum gain; pins 12, 13 and 14 grounded; VI(b-w) = 0.7 V; without load 2.5 2.8 3.1 V V30, 25, 20(max) maximum colour signal 4.0 4.5 5 V V30, 25, 20(min) V30, 25, 20(max) switch-off voltage (minimum output voltage level) maximum output voltage level at arbitrary input signals, contrast, brightness and gain adjustments; without load - VP - 2 0.05 - 0.1 VP - 1 V V R30, 25, 20 I30, 25, 20 output resistance maximum source current during fast positive signal transients during fast negative signal transients note 23 note 24 - -15 -40 - 44 - - - - - 80 - - - 50 - - - - 20 - 0.6 mA mA mA dB % I30, 25, 20M(source) peak source current I30, 25, 20M(sink) S/N D30, 25, 20(th) G30, 25, 20(f) tr(30, 25, 20) tf(30, 25, 20) dV30, 25, 20 peak sink current signal-to-noise ratio output thermal distortion Frequency response at signal outputs (channel 1: pin 30; channel 2: pin 25; channel 3: pin 20) amplification decrease by frequency response rise time of fast transients fall time of fast transients over/undershoot of output signal pulse related to actual output pulse amplitude f = 135 MHz (small signal) 10 to 90% amplitude; nominal colour signal; note 25 90 to 10% amplitude; nominal colour signal; note 25 input rise/fall time = 1 ns; nominal colour signal 1.2 2.7 3.9 5 3.0 3 4.3 10 dB ns ns % 1997 Nov 25 15 Philips Semiconductors Product specification 150 MHz video controller with I2C-bus TDA4885 SYMBOL ct(tr) ct(f) PARAMETER CONDITIONS MIN. TYP. - - - MAX. UNIT Crosstalk at signal outputs (channel 1: pin 30; channel 2: pin 25; channel 3: pin 20) transient crosstalk suppression input rise/fall time = 1 ns; note 26 crosstalk suppression by frequency f = 50 MHz f = 100 MHz 10 25 10 25 30 20 dB dB dB Internal feedback reference voltage; see Fig.15 and note 27 Vref(n) Vref(p) Vref/T Vref/VP internal reference voltage for negative feedback polarity fixed internal reference voltage for positive feedback polarity variation of Vref(n) and Vref(p) in the temperature range variation of Vref(n) and Vref(p) with supply voltage VP FFH; FPOL = 0 00H; FPOL = 0 FPOL = 1 Tamb = -20 to +70 C 7.6 V VP 8.8 V 3.8 5.6 0.6 0 0 4.0 5.8 0.7 - - 4.2 6.1 0.8 1.0 1.0 V V V % % External reference voltages (REF1: pin 32; REF2: pin 27; REF3: pin 22); see Fig.16 and note 28 V32, 27, 22 external reference voltage (equal to internal reference voltage with control bit FPOL = 0 ) variation of V32, 27, 22 in the temperature range variation of V32, 27, 22 with supply voltage VP output resistance maximum sink current maximum source current FFH 00H 3.8 5.6 4.0 5.8 4.2 6.1 V V V32, 27, 22/T V32, 27, 22/VP R32, 27, 22 I32, 27, 22 I32, 27, 22 I31, 26, 21(max) V30, 25, 20rbl(min) V30, 25, 20rbl(max) Vbl(CRT) Vbl(lf) Tamb = -20 to +70 C 7.6 V VP 8.8 V 0 0 - - - -500 0.01 0.01 2.4 2.4 0 - - - 90 - 1.0 1.0 - 400 % % A A -330 -280 -100 -60 0.1 0.1 2.8 2.8 40 0.1 0.5 0.5 4 4 200 0.5 Output clamping, feedback inputs (channel 1: pin 31; channel 2: pin 26; channel 3: pin 21) maximum input current minimum reference black level minimum pedestal black level maximum pedestal black level black level variation at CRT black level variation between clamping pulses related to nominal colour signal width of clamping pulse during output clamping; V11 > 3.5 V; V31, 26, 21 = 0.5 V PEDST = 0; V11 > 3.5 V PEDST = 1; V11 > 3.5 V PEDST = 1; V11 > 3.5 V note 29 line frequency 60 kHz; 10% duty cycle measured at V11 = 3 V; see Fig.8 nA V V V V mV % maximum reference black level PEDST = 0; V11 > 3.5 V tW11 td11(clamp)l 1 - - - - 300 s ns delay between clamping input see Fig.8 at pin 11 (leading edge) and start of internal output clamping pulse 16 1997 Nov 25 Philips Semiconductors Product specification 150 MHz video controller with I2C-bus TDA4885 SYMBOL td11(clamp)t PARAMETER delay between clamping input at pin 11 (trailing edge) and end of internal output clamping pulse CONDITIONS see Fig.8 - MIN. TYP. - MAX. 60 UNIT ns I2C-bus inputs (pins 15 and 16) fSCL VIL VIH IIL IIH VOL Iack Vth(POR)(r) Vth(POR)(f) SCL clock frequency LOW-level input voltage HIGH-level input voltage LOW-level input current HIGH-level input current LOW-level output voltage output current at pin 15 during acknowledge VIL = 0 V VIH = 5 V during acknowledge VOL = 0.4 V - 0.0 3.0 - - 0.0 3.0 - - - - - - - - - - - 1.5 3.5 - 1.5 100 1.5 5.0 -10 -10 0.4 5.0 2.0 - 7.0 - kHz V V A A V mA V V V V threshold for power-on reset on rising supply voltage falling supply voltage threshold for power-on reset off rising supply voltage falling supply voltage Notes to the characteristics 1. Definition of levels (see Figs 3 to 5): Reference black level: this is the level to which the input level is clamped during the input clamping pulse (V5 > 3.5 V). It is used internally as a reference for the gain settings. It can be observed on the outputs: a) when the input is at black and the brightness setting is nominal (subaddress 01H = 10H) b) during output blanking/clamping (V11 > 3.5 V) if control bit PEDST = 0. Video black level: this is the black level of the actual video. On the input it is still equal to the reference black level. On the output it may deviate from it according to the brightness setting. Contrast setting leaves the video black level unaltered . Pedestal black level: this is an ultra black level which deviates from reference black level by a fixed amount. It can be observed on the output during output blanking/clamping (V11 > 3.5 V) if control bit PEDST = 1. Switch-off voltage: this is the lowest signal voltage at outputs. The signals will be switched off by discharging the internal black level storage capacitors if the supply voltage is less than VPSO. Blanking level: this level equals reference black (control bit PEDST = 0) or pedestal black (control bit PEDST = 1). 2. Explanation to black level adjustment: The actual blanking level on the output depends on the external feedback application. The loop will only function correctly if it is within the control range of V30, 25, 20rbl(min) to V30, 25, 20rbl(max). Note: changing control bit PEDST in a given application will not affect the blanking level, but instead shifts the video (and needs re-alignment of the three black levels). The three reference black levels are aligned correctly when they are made equal to the `extended cut-off levels' of the three cathodes. Full raster and spot cut-off can only be achieved by enabling the pedestal blanking or by applying a negative pulse to grid 1. 1997 Nov 25 17 Philips Semiconductors Product specification 150 MHz video controller with I2C-bus 3. Definition of output signals (see Fig.6): Colour signal: all positive voltages referred to black level at signal outputs. TDA4885 Nominal colour signal: colour signal with nominal input signal (0.7Vb-w), nominal contrast setting and maximum gain setting. Video signal: all positive voltages referred to reference black level at signal outputs. The video signal is the superposing of the brightness information (Vbl) and the colour signal. 4. The total supply current IP = I7 + I29 + I24 + I19 depends on the supply voltage with a factor of approximately 10 mA/V and varies in the temperature range of -20 to +70 C by approximately 10% (V30, 25, 20 = 0.7 V). 5. The channel supply current depends on the signal output current, the channel supply voltage and the signal output voltage. With Ipx = I29, 24, 19 at VP1, 2, 3 = 8 V and V30, 25, 20 = 0.7 V: mA mA I 29, 24, 19 I px + I 30, 25, 20 + 3.1 -------- x ( V P1, 2, 3 - 8 V ) - 2.5 -------- x ( V 30, 25, 20 - 0.7 V ) V V 6. Pin 5 should be used for input clamping and blanking during vertical retrace (signal blanking, brightness blanking and if control bit PEDST = 1 pedestal blanking). With a fast clamping pulse (transition between V5 = 1.2 to 3.5 V and vice versa in less than 75 ns/V) no blanking will occur during input clamping. For 75 ns/V < tr/f5 280 ns/V the generation of the internal vertical blanking pulse is uncertain, for tr/f5 > 280 ns/V the internal blanking pulse will be generated. Pin 5 open-circuited will activate permanent input clamping and undefined blanking. 7. Input voltages less than -0.1 V can produce internal substrate currents which disturb the leakage currents at the signal inputs. An internal protection circuit creates a current for pin voltages of approximately 0 V or less. Feeding clamping/blanking pulses via a resistor of some k protects the pin from negative voltages. 8. Pin 11 should be used for output clamping and/or blanking. Pin 11 open-circuited will activate permanent blanking and output clamping. 9. The DC voltage during input clamping is temperature dependent with a factor of approximately 0.5 V/100 C (3VBE). 10. Composite signals will not disturb normal operations because an internal clipping circuit cuts all signal parts below input reference black level (see Fig.3). 11. Contrast control acts on internal colour signals under I2C-bus control; subaddress 02H (bit resolution 1.6% of contrast range). A 1 A 20 A 1 A 30 A 2 A 30 12. G track = 20 x maximum of log -------- x -------- ; log -------- x -------- ; log -------- x -------- dB A 10 A 2 A 10 A 3 A 20 A 3 Ax: colour signal output amplitude in channel x at any contrast setting. Ax0: colour signal output amplitude in channel x at nominal contrast and same gain setting. 13. When OSD fast blanking is active and V2, 3, 4 are HIGH (V1 > 1.7 V, V2, 3, 4 > 1.7 V) the OSD colour signals will be inserted in front of the gain potentiometers. This assures a correct grey scale of all video signals. The amplitudes of the inserted OSD signals can be controlled simultaneously by OSD contrast via I2C-bus. 14. Typical pulse at fast blanking input (pin 1) and response at signal outputs (pins 30, 25 and 20) with nominal input signals at pins 6, 8 and 10. 15. Typical pulse at fast blanking input (pin 1) as well as OSD inputs (pins 2, 3 and 4) and response at signal outputs (pins 30, 25 and 20) during OSD fast blanking for maximum OSD contrast, maximum gain adjustment and pins 12, 13 and 14 grounded. Small internal threshold and delay differences between fast blanking and signal insertion might cause short signal distortion at begin and end of signal insertion (see Fig.10). 16. OSD contrast control acts on inserted OSD colour signals under I2C-bus control; subaddress 03H (bit resolution 6.7% of OSD contrast range). 1997 Nov 25 18 Philips Semiconductors Product specification 150 MHz video controller with I2C-bus TDA4885 17. This pin can be used for beam current limiting or subcontrast setting. Both the video and OSD contrast are reduced simultaneously (see Figs 9 and 11). Because of the high-ohmic input impedance the pin should be tied to a voltage of more than 5 V or applied with a capacitor of some nF if not used. 18. Brightness control adds an I2C-bus controlled DC offset to the internal colour signal; subaddress 01H (bit resolution 1.6% of brightness range). 19. The voltage difference between video black level and reference black level is related to the colour signal with nominal 0.7 V (peak-to-peak value) input signal, at nominal contrast (subaddress 02H = 26H) and for any gain setting. The voltage difference is proportional to the gain setting (grey scale tracking). The given values of Vbl are valid only for video black levels higher than the signal output switch-off voltage V30, 25, 20(min). 20. Gain control acts on video signals and inserted OSD video signals under I2C-bus control; subaddress 04H (channel 1), 05H (channel 2) and 06H (channel 3; bit resolution 1.6% of gain range). 21. The usage of the gain modulation capability results in a reduction of the overall voltage gain of the TDA4885 but gives enough room for positive and negative modulation. Only pins 12, 13 and 14 connected to ground makes it possible to reach the specified maximum video signals at pins 30, 25 and 20 (see Fig.14). By short-circuiting pins 12, 13 and 14 it is possible to assure that the relations between the video signals remain constant for any modulation (common gain modulation). 22. Pedestal blanking produces an ultra black level during blanking and output clamping which is the most negative signal at the signal output pins. The reference black level which should correspond to the `extended cut-off voltage' at the cathodes is about V30, 25, 20PED higher (see Fig.5). The use of pedestal blanking with AC-coupled cathodes (control bit FPOL = 1) allows a very simple black level restoration with a DC diode clamp instead of a complicated pulse restoration circuit. 23. The signal-to-noise ratio is calculated by the formula (range 1 to 135 MHz): peak-to-peak value of the nominal signal output voltage S --- = 20 x log -------------------------------------------------------------------------------------------------------------------------------------------------- dB RMS value of the noise output voltage N 24. There might be short time smearing effects which have no thermal causes. The final amplitude will be reached some 10 ns after pulse step (amplitude differences of about 5%). For compensation methods see Section "Recommendations for building the application board" in Chapter "Test and application information". 25. Ideal input rise/fall time of 0 ns; t r, out = t r, ideal + t r, in 26. Crosstalk between any two output pins: a) Input conditions: any channel (channel A) with nominal input signal and 1 ns rise time. The inputs of the other two channels are capacitively coupled to ground (channel B). Gain setting to maximum (3FH). Contrast setting to nominal (26H) b) Output conditions: black level set to 1 V for each channel at signal outputs. Output signals are VA and VB respectively VA c) Transient crosstalk suppression: ct(tr) = 20 x log ------ dB VB 27. Internal feedback reference voltage acts under I2C-bus control for control bit FPOL = 0; subaddress 07H (channel 1), 08H (channel 2) and 09H (channel 3; bit resolution 0.4% of voltage range). The internal feedback reference voltages can be measured at feedback inputs (pins 31, 26 and 21) during output clamping (V11 > 3.5 V) in closed feedback loop. The feedback loop remains operative at output levels between typically 0.1 to 2.8 V. The reference voltages are not influenced by the value of control bit PEDST. The levels of the internal feedback reference voltages depend on the individual adjustments via I2C-bus (values from 00H to FFH) and the selected feedback polarity (control bit FPOL = 0 or 1): a) Control bit FPOL = 0: rising values of the data bytes (subaddresses 07H, 08H and 09H), e.g. 00H to FFH, correspond to rising values of the resulting reference black levels at signal outputs (pins 30, 25 and 20) b) Control bit FPOL = 1: the internal feedback reference voltage remains constant. 2 2 2 1997 Nov 25 19 Philips Semiconductors Product specification 150 MHz video controller with I2C-bus TDA4885 28. The external reference voltages act under I2C-bus control independent from control bit FPOL; subaddress 07H (REF1), 08H (REF2) and 09H (REF3; bit resolution 0.4% of voltage range). 29. Slow variations of video supply voltage VCRT will be suppressed at CRT cathode by the clamping feedback loop. A change of VCRT with 5 V leads to a specified change of the cathode voltage. handbook, full pagewidth input signals input video signal with syncs at pins 6, 8 and 10 input reference black level the syncs will be clipped to reference black level internally input clamping pulses at pin 5 blanking/output clamping pulses at pin 11 MHA344 The input video signals have to be on black level during input clamping. Fig.3 Input signals. 1997 Nov 25 20 Philips Semiconductors Product specification 150 MHz video controller with I2C-bus TDA4885 handbook, full pagewidth pulse, blanking output clamping pulse at pin 11 blanking signal output signals pins 30, 25 and 20 (1) maximum gain setting, nominal contrast setting, maximum/nominal/minimum brightness setting (2) (3) video black levels at maximum brightness nominal brightness minimum brightness reference black level switch-off voltage ground (1) (2) maximum gain setting, maximum brightness setting, maximum/nominal/minimum contrast setting (3) video black level (maximum brightness) reference black level switch-off voltage ground maximum brightness setting, nominal contrast setting, maximum/minimum gain setting (1) (3) video black level (maximum brightness) reference black level MHA345 switch-off voltage ground (1) Maximum. (2) Nominal. (3) Minimum. Fig.4 Definition of levels, function of brightness setting, contrast setting, gain setting, no pedestal blanking (PEDST = 0). 1997 Nov 25 21 Philips Semiconductors Product specification 150 MHz video controller with I2C-bus TDA4885 blanking handbook, full pagewidth pulse, output clamping pulse at pin 11 blanking signal output signals pins 30, 25 and 20 PEDST = 0 no pedestal blanking maximum gain setting, nominal contrast setting, maximum/minimum brightness setting (1) (2) video black levels at maximum brightness minimum brightness reference black level switch-off voltage ground PEDST = 1 pedestal blanking maximum gain setting, nominal contrast setting, maximum/minimum brightness setting (1) (2) video black levels at maximum brightness minimum brightness reference black level switch-off voltage ground pedestal black level MHA346 (1) Maximum. (2) Minimum. Fig.5 Output signals without (PEDST = 0) and with pedestal blanking (PEDST = 1). 1997 Nov 25 22 Philips Semiconductors Product specification 150 MHz video controller with I2C-bus TDA4885 handbook, output signals full pagewidth pins 30, 25 and 20 PEDST = 0 no pedestal blanking maximum gain setting, nominal contrast setting, maximum/minimum brightness setting colour signals video signals video black levels at maximum brightness minimum brightness reference black level MHA613 Fig.6 Definition of output signals. handbook, full pagewidth 3V input pulses at pin 5 trf5 75 ns/V 1.4 V internal pulse for input clamping tdl5 internal pulse for blanking tdt5 tdl5 MHA347 Fig.7 Timing of pulses at pin 5 and derived internal pulses. 1997 Nov 25 23 Philips Semiconductors Product specification 150 MHz video controller with I2C-bus TDA4885 handbook, full pagewidth 3V blanking signal at pin 11 1.4 V tW11 td11(cl)l td11(cl)t internal output clamping pulse 50% td11(sig)l blanking of output signal at pins 30, 25 and 20 at nominal brightness setting td11(br)l blanking of maximum brightness at pins 30, 25 and 20 brightness offset td11(sig)t colour signal 50% reference black level td11(br)t 50% reference black level MHA348 Fig.8 Delay between blanking input and output signal blanking, brightness blanking and output clamping. 1997 Nov 25 24 Philips Semiconductors Product specification 150 MHz video controller with I2C-bus TDA4885 handbook, full pagewidth MHA349 4 colour signal amplitude related to nominal colour signal amplitude (dB) 0 (2) (1) -28 00H 10H 20H 26H (3) 3FH 30H contrast control data byte (1) No contrast reduction by limiting. (2) Partial contrast reduction by limiting. (3) Full contrast reduction by limiting. Fig.9 Contrast control characteristic with limiting. 1997 Nov 25 25 Philips Semiconductors Product specification 150 MHz video controller with I2C-bus TDA4885 handbook, full pagewidth tf(FBL) tr(FBL) 90% 90% 10% 10% reference black level MHA932 a. Video signal with fast blanking at signal outputs (pins 30, 25 and 20). handbook, full pagewidth tr(OSD) tf(OSD) 90% 90% 10% 10% reference black level MHA933 b. OSD signal without video signal at signal outputs (pins 30, 25 and 20). handbook, full pagewidth dVOSD tg(CO) tg(OC) reference black level MHA934 c. Video signal with OSD signal insertion at signal outputs (pins 30, 25 and 20). Identical input pulse at pin 1 (fast blanking) and pins 2, 3 and 4 (OSD signal). Fig.10 OSD insertion. 1997 Nov 25 26 Philips Semiconductors Product specification 150 MHz video controller with I2C-bus TDA4885 handbook, full pagewidth 160 OSD signal amplitude related to nominal colour signal amplitude (%) maximum colour signal amplitude MHA351 125 maximum OSD signal amplitude 100 nominal colour signal amplitude (1) (2) 30 00H (3) 0FH OSD contrast control data byte (1) No OSD contrast reduction by limiting. (2) Partial OSD contrast reduction by limiting. (3) Full OSD contrast reduction by limiting. Fig.11 OSD contrast control characteristic with limiting. handbook, full pagewidth MHA352 30 difference of video black level and reference black level related to nominal colour signal amplitude (%) 0 (2) (1) -10 00H 10H 20H 30H brightness control data byte 3FH (1) Nominal adjustment. (2) Nominal brightness reference black level. Fig.12 Brightness control characteristic. 1997 Nov 25 27 Philips Semiconductors Product specification 150 MHz video controller with I2C-bus TDA4885 handbook, full pagewidth MHA353 1 video signal gain related to maximum video signal gain 0.45 0 00H 10H 20H 30H gain control data byte 3FH Fig.13 Gain control characteristic. handbook, full pagewidth MHA354 1 (1) (2) (3) (4) video signal gain related to 0.83 maximum video signal gain 0.68 0.45 0.31 0 00H 10H 20H 30H gain control data byte 3FH (1) (2) (3) (4) Pin 12, 13 or 14 grounded. 1 V at pin 12, 13 or 14. Open-circuit pin 12, 13 or 14. 3 V at pin 12, 13 or 14. Fig.14 Gain modulation. 1997 Nov 25 28 Philips Semiconductors Product specification 150 MHz video controller with I2C-bus TDA4885 handbook, full pagewidth MHA355 5.8 (1) internal feedback reference voltage (V) 4 (2) 0.7 0 00H 20H 40H 60H 80H A0H C0H E0H FFH feedback reference data byte (1) Control bit FPOL = 0. (2) Control bit FPOL = 1. Fig.15 Internal feedback reference voltages. handbook, full pagewidth MHA356 5.8 (1) external reference voltage (V) 4 0 00H 20H 40H 60H 80H A0H C0H E0H FFH feedback reference data byte (1) Control bit FPOL = 0 or 1. Fig.16 External feedback reference voltages. 1997 Nov 25 29 Philips Semiconductors Product specification 150 MHz video controller with I2C-bus 11 I2C-BUS PROTOCOL Table 1 Slave address A5(1) 0 A4(1) 0 A3(1) 0 A2(1) 1 A1(1) 0 A0(1) 0 TDA4885 A6(1) 1 Notes 1. Address bit. 2. Write bit. Table 2 S(1) Notes W(2) 0 Slave receiver format SLAVE ADDRESS A(2) SUBADDRESS A(3) DATA BYTE A(4) P(5) 1. START condition. 2. A = acknowledge. 3. All subaddresses within the range 00H to 09H are automatically incremented. The subaddress counter wraps around from 09H to 00H. The subaddress 0FH is reserved for test purposes under production. Do not use it. Subaddresses outside the range 00H to 0FH are acknowledged by the device but neither auto-increment nor any other internal operation takes place. 4. N data bytes with auto-increment of subaddresses. 5. STOP condition. 1997 Nov 25 30 Philips Semiconductors Product specification 150 MHz video controller with I2C-bus Table 3 Subaddress byte and data byte format FUNCTION Control register Brightness control Contrast control OSD contrast control Gain control channel 1 Gain control channel 2 Gain control channel 3 Black level reference channel 1 Black level reference channel 2 Black level reference channel 3 Reserved (note 5) Notes 1. The least significant bit (LSB) of an analog alignment register is defined as AX0 (data bit D0). 2. Data bit. SUBADDRESS 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0FH DATA BYTE(1) D7(2) X(4) X(4) X(4) X(4) X(4) X(4) X(4) A77 A87 A97 X(4) D6(2) X(4) X(4) X(4) X(4) X(4) X(4) X(4) A76 A86 A96 X(4) D5(2) X(4) A15 A25 X(4) A45 A55 A65 A75 A85 A95 X(4) D4(2) X(4) A14 A24 X(4) A44 A54 A64 A74 A84 A94 X(4) D3(2) A13 A23 A33 A43 A53 A63 A73 A83 A93 X(4) D2(2) A12 A22 A32 A42 A52 A62 A72 A82 A92 0 D1(2) A11 A21 A31 A41 A51 A61 A71 A81 A91 0 TDA4885 D0(2) A10 A20 A30 A40 A50 A60 A70 A80 A90 0 NOMINAL VALUE(3) - 10H 26H 0FH 3FH 3FH 3FH - - - - - FPOL DISV DISO PEDST 0AH to 0EH not used 3. After power-on reset control and test register are reset to logic 0 and all alignment registers are set to logic 0 (minimum). 4. X means don't care but for software compatibility with other video ICs with the same slave address, they are preferably set to logic 0. 5. For production tests only. Table 4 Control register BIT PEDST = 0 PEDST = 1 DISO = 0 DISO = 1 DISV = 0 DISV = 1 FPOL = 0 FPOL = 1 no pedestal blanking pedestal blanking enabled OSD signals enabled OSD signals disabled video signals enabled video signals disabled negative feedback polarity positive feedback polarity FUNCTION 1997 Nov 25 31 Philips Semiconductors Product specification 150 MHz video controller with I2C-bus TDA4885 handbook, full pagewidth START LOAD PRESET CONTROL BITS FPOL PEDST DISV = 1 DISO = 1 load from program ROM code or EEPROM LOAD FACTORY SETTINGS GAIN (CHANNEL 1, 2, 3) FEEDBACK REFERENCES (CHANNEL 1, 2, 3) load from EEPROM LOAD USER PRESET VALUES CONTRAST BRIGHTNESS OSD CONTRAST load from EEPROM no DEFLECTION CONTROL IC LOCKED yes DISV = 0 DISO = 0 DISPLAY NEW MODE (1) DISO = 1 USER INPUT no yes DISO = 0 RESPONSE TO USER INPUTS (CONTRAST, BRIGHTNESS, OSD CONTRAST) DISO = 1 (1) Only synchronized video should be displayed. Each new mode can be displayed by OSD. It is recommended to synchronize data transmission (brightness, contrast and OSD contrast) with vertical blanking pulse. DEFLECTION CONTROL IC LOCKED yes no DISV = 1 MHA614 Fig.17 I2C-bus control flow. 1997 Nov 25 32 1997 Nov 25 33 Philips Semiconductors 12 INTERNAL CIRCUITRY 150 MHz video controller with I2C-bus PIN 1 SYMBOL AND DESCRIPTION FBL; fast blanking input for OSD insertion CHARACTERISTIC open-circuit base WAVEFORM 5V VP 0V MHA653 EQUIVALENT CIRCUIT 50 A signal blanking 1 1 k 50 A OSD1 blanking 50 A OSD2 blanking 50 A OSD3 blanking MHA928 2 OSD1; OSD input channel 1 V2 < VP - 1 V: open-circuit base 5V VP 50 A 0V MHA653 V2 = VP: I2 = 85 to 210 A test current VP 2 1 k signal blanking disable OSD 1 k FBL MHA929 Product specification TDA4885 1997 Nov 25 34 Philips Semiconductors PIN 3 SYMBOL AND DESCRIPTION OSD2; OSD input channel 2 150 MHz video controller with I2C-bus CHARACTERISTIC V3 < VP - 1 V: open-circuit base WAVEFORM 5V EQUIVALENT CIRCUIT VP 50 A 0V MHA653 V3 = VP: I3 = 80 to 280 A test current VP 3 1 k signal blanking disable OSD 1 k FBL MHA930 4 OSD3; OSD input channel 3 V4 < VP - 1 V: open-circuit base 5V VP 50 A 0V MHA653 V4 = VP: I4 = 80 to 280 A test current VP 4 1 k signal blanking disable OSD 1 k FBL MHA931 Product specification TDA4885 1997 Nov 25 35 Philips Semiconductors PIN 5 SYMBOL AND DESCRIPTION CLI; vertical blanking input (input clamping) 150 MHz video controller with I2C-bus CHARACTERISTIC V5 > 0.2 V: open-circuit base WAVEFORM 5V 2.5 V 0V MHA651 EQUIVALENT CIRCUIT 2VBE 6 k VP 10 k 26 A 3 V + VBE V5 0.2 V: source current rising with decreasing voltage VP 5 1 k 10 k power on/down MHA619 6 VI1; signal input channel 1 outside clamping pulse: open-circuit base with base current compensation 4.7 V black shoulder VP video signal sync 4V 3.7 V 6 MIRROR 1:1 VP during clamping: I6 = -150 to +150 A input clamping (pin 5) MHA652 700 1.8 V + VBE signal 150 A 0 A MHA620 240 A 220 A Product specification 7 VP; supply voltage 20 mA 7 TDA4885 MHA621 1997 Nov 25 36 Philips Semiconductors PIN 8 SYMBOL AND DESCRIPTION VI2; signal input channel 2 150 MHz video controller with I2C-bus CHARACTERISTIC outside clamping pulse: open-circuit base with base current compensation WAVEFORM 4.7 V black shoulder VP video signal sync 4V 3.7 V 8 EQUIVALENT CIRCUIT MIRROR 1:1 VP during clamping: I6 = -150 to +150 A input clamping (pin 5) MHA652 700 1.8 V + VBE signal 150 A 0 A MHA622 240 A 220 A 9 GND; ground 9 MHA623 10 VI3; signal input channel 3 outside clamping pulse: open-circuit base with base current compensation 4.7 V black shoulder VP video signal sync 4V 3.7 V 10 MIRROR 1:1 VP during clamping: I6 = -150 to +150 A input clamping (pin 5) MHA652 700 1.8 V + VBE signal 150 A 0 A MHA624 Product specification 240 A 220 A TDA4885 1997 Nov 25 37 Philips Semiconductors PIN 11 SYMBOL AND DESCRIPTION HFB; horizontal flyback input (output clamping, blanking) 150 MHz video controller with I2C-bus CHARACTERISTIC V11 > 0.2 V: open-circuit base WAVEFORM 5V 0V MHA649 EQUIVALENT CIRCUIT 2VBE 6 k VP 10 k 27 A clamping 27 A blanking 12 k V11 0.2 V: source current rising with decreasing voltage VP 3 V + VBE 1 k 1.7 V 10 k 11 power on/down MHA625 12 GM1; gain modulation input channel 1 R12 = 20 k; open-circuit voltage V12 = 2.0 V MHA650 3V 2V 1V 5.5 V 27.5 k 2.2 V VP 12 10 k 15.7 k MHA626 13 GM2; gain modulation input channel 2 R13 = 20 k; open-circuit voltage V13 = 2.0 V MHA650 3V 2V 1V 5.5 V 27.5 k 2.2 V VP Product specification TDA4885 13 10 k 15.7 k MHA627 1997 Nov 25 38 Philips Semiconductors PIN 14 SYMBOL AND DESCRIPTION GM3; gain modulation input channel 3 150 MHz video controller with I2C-bus CHARACTERISTIC R14 = 20 k; open-circuit voltage V14 = 2.0 V WAVEFORM 3V 2V 1V MHA650 EQUIVALENT CIRCUIT 5.5 V 27.5 k 2.2 V VP 14 10 k 15.7 k MHA628 15 SDA; I2C-bus serial data input/output no acknowledge; open-circuit base during acknowledge: I15 = 4 mA 5V 0V MHA647 3 A 70 A 19 A 10 k 15 2.46 V + VBE MHA629 acknowledge 16 SCL; I2C-bus clock input open-circuit base 5V 0V 10 k MHA648 19 A 16 2.46 V + VBE MHA630 Product specification TDA4885 1997 Nov 25 39 Philips Semiconductors PIN 17 SYMBOL AND DESCRIPTION LIM; beam current limiting input 150 MHz video controller with I2C-bus CHARACTERISTIC open-circuit voltage V17 = 5.0 V WAVEFORM VP EQUIVALENT CIRCUIT 21 A 1 k 5.0 V 10 k 17 V17 < 4.5 V: open-circuit base MHA631 18 GND3; ground channel 3 VP3; supply voltage channel 3 I19 = 40 mA 18 MHA632 19 19 MHA633 Product specification TDA4885 1997 Nov 25 40 Philips Semiconductors PIN 20 SYMBOL AND DESCRIPTION VO3; signal output channel 3 150 MHz video controller with I2C-bus CHARACTERISTIC reference black level 0.1 to 2.8 V WAVEFORM MHA655 EQUIVALENT CIRCUIT VP VP 500 brightness 20 reference black level during output clamping 80 8 k 1.5 k 3.5 pF control bit PEDST = 0 pedestal black level 0.1 to 2.8 V brightness MHA656 MHA634 pedestal black level during output clamping control bit PEDST = 1 21 FB3; feedback input channel 3 open-circuit base feedback reference 5.8 to 4 V VP 10 A PEDST = 0 21 1 k 15 k PEDST = 1 MHA654 10 A Vs1 15 k Vs2 1 k 1 k MHA635 control bit FPOL = 0 0.7 V PEDST = 1 DC coupling; Vs1 = 0 V; Vs2 = 1 V (control bit FPOL = 0) AC coupling; Vs1 = 1 V; Vs2 = 0 V (control bit FPOL = 1) PEDST = 0 5.8 to 4 V Product specification TDA4885 feedback reference 0.7 V MHA660 control bit FPOL = 1 1997 Nov 25 41 Philips Semiconductors PIN 22 SYMBOL AND DESCRIPTION REF3; reference voltage channel 3 150 MHz video controller with I2C-bus CHARACTERISTIC -300 to +300 A WAVEFORM VP EQUIVALENT CIRCUIT 300 A 170 15 A 22 5.8 to 4 V 30 A 7.5 A MHA636 23 GND2; ground channel 2 VP2; supply voltage channel 2 I24 = 40 mA 23 MHA637 24 24 MHA638 Product specification TDA4885 1997 Nov 25 42 Philips Semiconductors PIN 25 SYMBOL AND DESCRIPTION VO2; signal output channel 2 150 MHz video controller with I2C-bus CHARACTERISTIC reference black level 0.1 to 2.8 V WAVEFORM MHA655 EQUIVALENT CIRCUIT VP VP 500 brightness 25 reference black level during output clamping 80 8 k 1.5 k 3.5 pF control bit PEDST = 0 pedestal black level 0.1 to 2.8 V brightness MHA656 MHA639 pedestal black level during output clamping control bit PEDST = 1 26 FB2; feedback input channel 2 open-circuit base feedback reference 5.8 to 4 V VP 10 A PEDST = 0 26 1 k 15 k PEDST = 1 MHA654 10 A Vs1 15 k Vs2 1 k 1 k MHA640 control bit FPOL = 0 0.7 V PEDST = 1 DC coupling; Vs1 = 0 V; Vs2 = 1 V (control bit FPOL = 0) AC coupling; Vs1 = 1 V; Vs2 = 0 V (control bit FPOL = 1) PEDST = 0 5.8 to 4 V Product specification TDA4885 feedback reference 0.7 V MHA660 control bit FPOL = 1 1997 Nov 25 43 Philips Semiconductors PIN 27 SYMBOL AND DESCRIPTION REF2; reference voltage channel 2 150 MHz video controller with I2C-bus CHARACTERISTIC -300 to +300 A WAVEFORM VP EQUIVALENT CIRCUIT 300 A 170 15 A 27 5.8 to 4 V 30 A 7.5 A MHA641 28 GND1; ground channel 1 VP1; supply voltage channel 1 I29 = 40 mA 28 MHA642 29 29 MHA643 Product specification TDA4885 1997 Nov 25 44 Philips Semiconductors PIN 30 SYMBOL AND DESCRIPTION VO1; signal output channel 1 150 MHz video controller with I2C-bus CHARACTERISTIC reference black level 0.1 to 2.8 V WAVEFORM MHA655 EQUIVALENT CIRCUIT VP VP 500 brightness 30 reference black level during output clamping 80 8 k 1.5 k 3.5 pF control bit PEDST = 0 pedestal black level 0.1 to 2.8 V brightness MHA656 MHA644 pedestal black level during output clamping control bit PEDST = 1 31 FB1; feedback input channel 1 open-circuit base feedback reference 5.8 to 4 V VP 10 A PEDST = 0 31 1 k 15 k PEDST = 1 MHA654 10 A Vs1 15 k Vs2 1 k 1 k MHA645 control bit FPOL = 0 0.7 V PEDST = 1 DC coupling; Vs1 = 0 V; Vs2 = 1 V (control bit FPOL = 0) AC coupling; Vs1 = 1 V; Vs2 = 0 V (control bit FPOL = 1) PEDST = 0 5.8 to 4 V Product specification TDA4885 feedback reference 0.7 V MHA660 control bit FPOL = 1 1997 Nov 25 45 Philips Semiconductors PIN 32 SYMBOL AND DESCRIPTION REF1; reference voltage channel 1 150 MHz video controller with I2C-bus CHARACTERISTIC -300 to +300 A WAVEFORM VP EQUIVALENT CIRCUIT 300 A 170 15 A 32 5.8 to 4 V 30 A 7.5 A MHA646 Product specification TDA4885 Philips Semiconductors Product specification 150 MHz video controller with I2C-bus 13 TEST AND APPLICATION INFORMATION TDA4885 handbook, full pagewidth fast blanking 1 32 n.c. VCRT = 90 V 2 31 OSD inputs 3 30 to cathode 4 input clamping vertical blanking 29 5 28 VCRT = 70 V 6 27 BLACK LEVEL RESTORATION to cathode 7 signal inputs 26 8 25 TDA4885 9 24 23 10 VCRT = 90 V n.c. 11 22 output clamping blanking 12 21 20 13 to cathode 14 19 15 18 16 17 GND beam current limiting; subcontrast setting I2C-BUS VP = 8 V MHA927 Fig.18 Basic application for different output stages with DC coupling (FPOL = 0) or AC coupling (FPOL = 1). 1997 Nov 25 46 Philips Semiconductors Product specification 150 MHz video controller with I2C-bus 13.1 Test application TDA4885 The beam current limiting pin is fed to the 10-pin main connector without any special application and should be connected to the 5 V supply if not used. DC supply voltage VP with a series resistor of 5.6 can be measured directly at pin 7 via a resistor of 1 k (VP sense). The supply voltage for the signal channels is fed to VPX separately and connected to pins 19, 24 and 29 with decoupling resistors of 5.6 . The supply voltage VP1 (pin 29) can be measured via 1 k at pin VP1 sense. All supply voltages are filtered near to their pins with 150 pF and 100 nF SMD capacitors and low impedance 0.47 F/63 V electrolytic capacitors. The signal outputs are loaded with 10 k and 3 pF to ground and are connected to a probe socket. With a probe capacitance of 2 pF the total capacitive load is 5 pF. The feedback inputs are connected to the voltage outputs with a 0 resistor (short circuit; RFB1) and via 10 k (RFB2) connected to the pin VFBDC. The blanking level can be adjusted with a variation of RFB1, RFB2 and VFBDC but the resistive output load will be changed. The blanking level is: RFB1 RFB1 U outbl = 1 + --------------- x 0.7 V - --------------- x VFBDC RFB2 RFB2 The reference outputs are connected to solder pins. For high frequency measurements a special test application and printed-circuit board with only a few external components is built. Figure 19 shows the test application circuit and Figs 20 and 21 the layout of the double sided printed board. Most components are of SMD type. Short HF loops and minimum crosstalk between the channels and between signal inputs and outputs are achieved by properly shaped ground areas. The HF input signal can be fed to the subclick connectors VI1, VI2 and VI3 by a 50 line. The line is then terminated by a 50 resistor on the board. In channel 3 (pin 10) the HF input signal can be measured (probe socket). For operation without input clamping the DC bias can be provided by VINDC if a short-circuit at J1, J2 and J3 is made. OSD input signals (subclick: OSD1, OSD2, OSD3, FBL) and blanking/clamping inputs (subclick: CLI, HFB) are terminated with 50 on the board. The gain modulation input GM (subclick) can be connected to the three inputs by the jumpers J8 and J4, J5 and J6. With jumper J7 pins 12, 13 and 14 can be connected to ground (no gain reduction). There is a separate 4-pin connector for the I2C-bus controller, SDA and SCL have 10 k pull up resistors to 5 V digital supply. 1997 Nov 25 47 Philips Semiconductors Product specification 150 MHz video controller with I2C-bus TDA4885 handbook, full pagewidth 5.6 FBL 50 1 k FBL 1 32 REF1 OSD1 OSD1 50 OSD2 50 OSD3 50 CLI 10 nF 50 VI1 50 150 pF 10 nF 5 k VP J1 0.47 F (63 V) 5 k GND J2 VI3 50 150 pF 5 k probe J3 50 GM1 J4 GM2 J5 J7 HFB 100 nF 100 pF VI2 2 31 FB1 OSD2 3 30 VO1 1 k channel 1 VP1 5.6 GND1 VO1 OSD3 4 29 CLI 5 28 VI1 6 27 REF2 solder pin 10 k RFB2 10 k RFB1 channel 2 VO2 10 k 150 pF 100 nF 0.47 F (63 V) 3 pF 5.6 7 26 FB2 VI2 50 150 pF 10 nF VI3 8 25 VO2 TDA4885 9 24 VP2 10 23 GND2 11 22 REF3 HFB 12 21 FB3 13 20 VO3 channel 3 VO3 GM GM3 J6 SDA 14 19 VP3 J8 VPX VP1 sense VFBDC VP sense VP GND VINDC 15 18 GND3 10 k SDA 5V SCL MHA657 SCL 10 k 16 17 LIM LIM 5V Fig.19 Test board. 1997 Nov 25 48 Philips Semiconductors Product specification 150 MHz video controller with I2C-bus TDA4885 handbook, full pagewidth 76.20 116.84 OSD3 OSD2 OSD1 FBL 5.6 CLI 100 nF 150 pF J1 IC1 MP 10 k 10 k 3.3 pF MP 10 k 10 k 3.3 pF MP 10 k 10 k 3.3 pF 10 k 0.47 F 10 k 0.47 F 10 k 0.47 F VO2 TP VO1 JP TP 1 k VI1 J2 VI2 J3 VI3 0.47 F TP SDA VP GND SCL J6 I2C-bus J7 J8 TP J5 GM HFB MHA658 J4 VO3 Fig.20 Component layout and printed-circuit board; side A (for side B see Fig.21). 1997 Nov 25 49 Philips Semiconductors Product specification 150 MHz video controller with I2C-bus TDA4885 handbook, full pagewidth 76.20 116.84 50 50 50 50 50 1 k 5.6 5.6 150 pF 100 nF 100 nF 100 nF 150 pF 150 pF 100 nF 150 pF 10 k 50 10 k 5 k 10 nF 150 pF 5 k 10 nF 150 pF 5 k 10 nF 150 pF 50 50 50 5.6 MHA659 Fig.21 Component layout and printed-circuit board; side B (for side A see Fig.20). 1997 Nov 25 50 Philips Semiconductors Product specification 150 MHz video controller with I2C-bus 13.2 Recommendations for building the application board TDA4885 * General - Double-sided board - Short HF loops by large ground plane on the rear - SMD components with minimum parasitics. * Voltage outputs - Capacitive loads as small as possible - Be aware of internal output resistance (80 ). * Supply voltages - Capacitors as near as possible to the pins - Use electrolytic capacitors with small serial resistance and inductance. * Smearing - Additional peaking circuit at emitter of driver transistor of cascode stage (time constant approximately 100 ns). 1997 Nov 25 51 Philips Semiconductors Product specification 150 MHz video controller with I2C-bus 14 PACKAGE OUTLINE SDIP32: plastic shrink dual in-line package; 32 leads (400 mil) TDA4885 SOT232-1 D seating plane ME A2 A L A1 c Z e b 32 17 b1 wM (e 1) MH pin 1 index E 1 16 0 5 scale 10 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 4.7 A1 min. 0.51 A2 max. 3.8 b 1.3 0.8 b1 0.53 0.40 c 0.32 0.23 D (1) 29.4 28.5 E (1) 9.1 8.7 e 1.778 e1 10.16 L 3.2 2.8 ME 10.7 10.2 MH 12.2 10.5 w 0.18 Z (1) max. 1.6 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT232-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 92-11-17 95-02-04 1997 Nov 25 52 Philips Semiconductors Product specification 150 MHz video controller with I2C-bus 15 SOLDERING 15.1 Introduction TDA4885 with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. 15.3 Repairing soldered joints There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). 15.2 Soldering by dipping or by wave The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact 16 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds. This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications. Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 17 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale 18 PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 1997 Nov 25 53 Philips Semiconductors Product specification 150 MHz video controller with I2C-bus NOTES TDA4885 1997 Nov 25 54 Philips Semiconductors Product specification 150 MHz video controller with I2C-bus NOTES TDA4885 1997 Nov 25 55 Philips Semiconductors - a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 160 1010, Fax. +43 160 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 689 211, Fax. +359 2 689 102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. +45 32 88 2636, Fax. +45 31 57 0044 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615800, Fax. +358 9 61580920 France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex, Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 23 53 60, Fax. +49 40 23 536 300 Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS, Tel. +30 1 4894 339/239, Fax. +30 1 4814 240 Hungary: see Austria India: Philips INDIA Ltd, Band Box Building, 2nd floor, 254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025, Tel. +91 22 493 8541, Fax. +91 22 493 0966 Indonesia: see Singapore Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3, 20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. +27 11 470 5911, Fax. +27 11 470 5494 South America: Al. Vicente Pinzon, 173, 6th floor, 04547-130 SAO PAULO, SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 821 2382 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 3 301 6312, Fax. +34 3 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 632 2000, Fax. +46 8 632 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2686, Fax. +41 1 481 7730 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2865, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Talatpasa Cad. No. 5, 80640 GULTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777 For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1997 Internet: http://www.semiconductors.philips.com SCA56 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 547047/1200/02/pp56 Date of release: 1997 Nov 25 Document order number: 9397 750 02705 |
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